A sigma-delta (ΣΔ) modulation A/D converter may improve the bit accuracy of the pass-band due to the effects of oversampling and noise shaping.
The oversampling refers to the sampling of an analog signal at a high sampling rate that is a multiple of several tens to several hundreds the sampling rate necessary for the pass-band. FIGS. 1A and 1B are diagrams for explaining scattering of quantization noise by oversampling. In FIGS. 1A and 1B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. Further, fs1 denotes the sampling frequency before the oversampling, and fs2 denotes the sampling frequency after the oversampling. The noise illustrated in FIG. 1A may be scattered by the oversampling such that the quantization noise having a total amount that is constant is scattered in the wider frequency band illustrated in FIG. 1B, in order to obtain the effect of reducing the amount of noise included in the pass-band.
The noise shaping refers to the shaping and shifting of the quantization noise having a flat distribution into the high-frequency range. The ΣΔ modulator performs the noise shaping using a feedback circuit, but the noise shaping characteristic or the sharpness of the noise waveform after the noise shaping may be varied by the circuit structure thereof.
FIGS. 2A and 2B are diagrams for explaining an example of a first order ΣΔ modulation A/D converter that is used in a ΣΔ modulation A/D converter. FIG. 2A illustrates the structure of the first order ΣΔ modulator, and FIG. 2B illustrates a noise waveform after noise shaping by the first order ΣΔ modulator. In FIG. 2B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. The first order ΣΔ modulator includes adders 1 and 2, an integrator 3, a comparator 4, and a 1-bit D/A converter 5 that are connected as illustrated in FIG. 2A. A digital output data Y(z) of the first order ΣΔ modulator with respect to an analog input data X(z) may be represented by Y(z)=z−1X(z)+(1−z−1)Q(z), and the value of the noise shaping of the noise waveform corresponds to the term (1−z−1)Q(z), where Q(z) denotes the quantization noise.
FIGS. 3A and 3B are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in the ΣΔ modulation A/D converter. FIG. 3A illustrates the structure of the second order ΣΔ modulator, and FIG. 3B illustrates a noise waveform after noise shaping by the second order ΣΔ modulator. In FIG. 3B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the sampling frequency in arbitrary units. The second order ΣΔ modulator includes adders 1, 2, 11 and 12, integrators 3 and 13, a comparator 4, a 1-bit D/A converter 5, and a multiplier 15 that are connected as illustrated in FIG. 3A. A digital output data Y(z) of the second order ΣΔ modulator with respect to an analog input data X(z) may be represented by Y(z)=z−2X(z)+(1−z−1)2Q(z), and the value of the noise shaping of the noise waveform corresponds to the term (1−z−1)2Q(z), where Q(z) denotes the quantization noise.
The ΣΔ modulation A/D converter may have a structure including the ΣΔ modulator illustrated in FIG. 2 or FIG. 3, a digital lowpass filter (not illustrated), and a decimator (not illustrated), for example. In this case, the digital lowpass filter eliminates the quantization noise that is shifted in the high-frequency range by the ΣΔ modulator. The decimator decimates the output data of the digital lowpass filter, that has been eliminated of the quantization noise, in order to convert the analog data input to the ΣΔ modulator into high-precision digital data.
The ΣΔ modulator is also applicable to a ΣΔ modulation D/A converter. FIG. 4 are diagrams for explaining an example of a second order ΣΔ modulation A/D converter that is used in the ΣΔ modulation D/A converter. FIG. 4A illustrates digital data input to the ΣΔ modulator, and FIG. 4B illustrates the structure of the ΣΔ modulator. The ΣΔ modulator includes adders 21, 22, 31 and 32, integrators 2 and 33, a comparator 24, a 16-bit A/D converter 25, and a multiplier 35 that are connected as illustrated in FIG. 4B. Q(z) denotes the quantization noise.
The digital data is input to the ΣΔ modulator, and the analog data is output from the ΣΔ modulator. The ΣΔ modulation D/A converter may have a structure including the ΣΔ modulator illustrated in FIG. 4B, an interpolator (not illustrated), and a D/A conversion and lowpass filter part (not illustrated), for example. In this case, the digital data input to the ΣΔ modulator is oversampled at a high rate by an interpolation performed by the interpolator. For example, the 16-bit digital data is converted into data of 1 bit or several bits by the digital processing of the ΣΔ modulator, in order to form a ΣΔ modulation D/A converter that is uneasily affected by inconsistencies in the characteristics of analog elements. In addition, the high-frequency noise within the digital data may easily be eliminated by the D/A conversion and lowpass filter part.
The ΣΔ modulation A/D converter and the ΣΔ modulation D/A converter using the ΣΔ modulator described above may be utilized in various fields including audio equipments and measuring equipments, where high-precision A/D conversion or high-precision D/A conversion is required.
FIG. 5 is a diagram for explaining an example of the ΣΔ modulation A/D converter using the ΣΔ modulator. The ΣΔ modulation A/D converter includes an analog part 41 and a digital part 42. The analog part 41 includes a ΣΔ modulator 411, a Delay Flip-Flip (D-FF) 412, and a level converting part 413 including level converters 4131 and 4132, which are connected as illustrated in FIG. 5. The level converter 4131 is provided with respect to a clock signal, and the level converter 4132 is provided with respect to ΣΔ modulated data. The digital part 42 includes a lowpass filter 421, and a decimator 422 which are connected as illustrated in FIG. 5. For example, a power supply voltage Va=5.0 V is supplied to the analog part 41, and a power supply voltage Vd=1.8 V is supplied to the digital part 42. In FIG. 5, GNDa denotes the ground for the analog part 41, and GNDd denotes the ground for the digital part 42. The level converting part 412 receives both the power supply voltage Va and the power supply voltage Vd.
FIG. 6 is a diagram for explaining an example of the ΣΔ modulation D/A converter using the ΣΔ modulator. The ΣΔ modulation D/A converter includes a digital part 51 and an analog part 52. The digital part 51 includes an interpolator 511, a ΣΔ modulator 512, and a D-FF 513 which are connected as illustrated in FIG. 6. In addition, the analog part 52 includes a level converting part 521, a D-FF 522, and a D/A conversion and lowpass filter part 523 which are connected as illustrated in FIG. 6. The level converting part 521 includes a level converter provided with respect to the clock signal, and a level converter provided with respect to the ΣΔ modulated data, similarly to the level converting part 413 illustrated in FIG. 5. For example, the power supply voltage Vd=1.8 V is supplied to the digital part 51, and the power supply voltage Va=5.0 V is supplied to the analog part 52. GNDd denotes the ground for the digital part 51, and GNDa denotes the ground for the analog part 52. The level converting part 521 receives both the power supply voltage Va and the power supply voltage Vd.
In the circuits illustrated in FIGS. 5 and 6 in which the analog part and the digital part coexist, the ground GNDa for the analog part and the ground GNDd for the digital part may be provided separately for the purposes of reducing the noise or reducing the power consumption. In this case, a level converting part is provided at an interface, and a delay circuit, such as a D-FF, is provided for clock signal synchronization. However, in the level converting part and the D-FF, a relatively large current may flow for an instant at a data transition point where the input data value makes a transition from “0” to “1” or makes a transition from “1” to “0”, and the relatively large current may cause power supply noise of the power supply or the ground.
FIGS. 7A, 7B, and 7C are diagrams for explaining an example of the power supply noise generated at the data transition point. FIG. 7A illustrates the input data to the level converting part (413 or 521), and the power supply noise with respect to the analog part (41 or 52). FIG. 7B illustrates the input clock signal and the input data with respect to the D-FF (412 or 513), and the power supply noise with respect to the analog part (41 or 52). In FIGS. 7A and 7B, the ordinate indicates the signal level in arbitrary units, and the abscissa indicates the time in arbitrary units. In addition, FIG. 7C illustrates the ΣΔ modulated data output from the ΣΔ modulator (411 or 512), and a relative value of the amount of power supply noise with respect to the analog part (41 or 52).
The power supply noise with respect to the analog part includes a frequency component different from that of the ΣΔ modulated data, but as may be seen from FIGS. 8 through 10, the power supply noise component is dependent on the input data frequency or the clock signal frequency. FIG. 8 is a diagram illustrating an example of a ΣΔ modulated data spectrum for a case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. FIG. 9 is a diagram illustrating an example of a power supply noise spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the relative value of the noise level and the abscissa indicating the frequency. FIG. 10 is a diagram illustrating an example of an output signal spectrum affected by power supply noise for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. In FIG. 8 and the like, a 32 k-mode signal is subjected to a 64-times oversampling, for example, and the oversampling frequency is 2.048 MHz.
In the ΣΔ modulation A/D converter, the power supply noise may generate an error in the sampling value of the input analog data. In this case, the ΣΔ modulated data may include the power supply noise component.
On the other hand, in the ΣΔ modulation D/A converter, the power supply noise may mix into the output analog data. In this case, if the ΣΔ modulation D/A converter is used in an audio equipment, for example, the power supply noise that mixes into the output analog data may be heard as non-negligible noise.
Recently, a method has been proposed to output a multi-valued output having three or more values from the comparator of the ΣΔ modulator, instead of a binary output that is “0” or “1”, particularly for use in the ΣΔ modulation D/A converter. When the multi-valued output having three or more values is output from the comparator, it is possible to reduce the noise component corresponding to the term (1−z−1)Q(z) in FIGS. 2A and 2B. FIGS. 11A and 11B are diagrams for explaining quantization noise for a case where the comparator output is the binary output and a 11-valued output, with the amount of noise indicated in arbitrary units. FIG. 11A illustrates the quantization noise Q for the case where the binary output is output from the comparator, and FIG. 11B illustrates the quantization noise Q for the case where the 11-valued output is output from the comparator. As may be seen from a comparison of FIGS. 11A and 11B, the amount of the quantization noise Q for the 11-valued output of the comparator is smaller than the amount of the quantization noise Q for the binary output of the comparator.
However, the inconsistencies in the characteristics of the analog elements, which do not greatly affect the ΣΔ modulation D/A converter when the comparator outputs the binary output, may cause non-negligible effects when the comparator outputs the multi-valued output having three or more values. For this reason, it may be desirable to average the inconsistencies in the characteristics of the analog elements by employing a technique such as the Dynamic Element Matching (DEM). In one example of the DEM, the analog element that is used is shifted one analog element at a time, as illustrated in FIG. 12A. FIGS. 12A and 12B are diagrams for explaining an example of the DEM. FIG. 12A illustrates the ΣΔ modulated data, and FIG. 12B illustrates the power supply noise. In FIGS. 12A and 12B, it is assumed for the sake of convenience that the ΣΔ modulated data includes 10 bits DT01 through DT10, and the value of the ΣΔ modulated data changes as MD1→MD2→MD3→MD4, that is, changes as 4→5→5→4.
When the value of the ΣΔ modulated data changes as MD1→MD2, a number of logic inversions (or the amount of data change) becomes “3” as indicated by hatching in FIG. 12A. When the ΣΔ modulation changes as MD2→MD3, the number of logic inversions becomes “2” as indicated by the hatching in FIG. 12A. In addition, when the value of the ΣΔ modulated data changes from MD3→MD4, the number of logic inversions becomes “1”, as indicated by the hatching in FIG. 12A. FIG. 12B illustrates the power supply noise for the case where the number of logic inversions is “3”, “2”, and “1”. In FIG. 12B, the ordinate indicates the noise level in arbitrary units, and the abscissa indicates the time in arbitrary units.
When the multi-valued output of the comparator has three or more values, the number of level converting parts, the number of the D-FFs and the like that are used become larger than those used in the case where the comparator outputs the binary output. Consequently, the circuit scale increases even when the DEM or the like is employed, and the power supply noise tends to increase with the increase in the circuit scale for the case where the comparator outputs the multi-valued output having three or more values. The power supply noise component for the case where the comparator outputs the multi-valued output having three or more values is dependent on the input data frequency or the clock signal frequency, similarly to the case where the comparator outputs the binary output, as may be seen from FIGS. 13 through 15 which illustrate the case where the comparator outputs the 11-valued output. FIG. 13 is a diagram illustrating an example of a ΣΔ modulated data spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency. FIG. 14 is a diagram illustrating an example of a power supply noise spectrum for the case where the input data frequency is 1020 Hz, with the ordinate indicating the relative value of the noise level and the abscissa indicating the frequency. In addition, FIG. 15 is a diagram illustrating an example of an output signal spectrum affected by the power supply noise for the case where the input data frequency is 1020 Hz, with the ordinate indicating the signal level and the abscissa indicating the frequency.
Japanese Laid-Open Patent Publications No. 6-232857 and No. 3-101411 disclose the ΣΔ modulation A/D and/or D/A converter.
According to the above-described A/D converters and D/A converters, it is difficult to reduce the noise.